An efficient design of fractional-delay digital FIR filters using the Farrow structure

IEEE Workshop on Statistical Signal Processing Proceedings

Volumn , Issue , 2001, Pages 595-598

  Pun, Carson K S ^a   Wu, Y C ^a   Chan, S C ^a   Ho, K L ^a  

^a UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; INTERPOLATION; MULTIPLYING CIRCUITS; PHASE CONTROL; POLYNOMIAL APPROXIMATION; SIGNAL FILTERING AND PREDICTION; TUNING; VLSI CIRCUITS;

FRACTIONAL-DELAY DIGITAL FILTERS (FD-DF);

FIR FILTERS;

EID: 0035556279     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A continuously variable digital delay element
2. Efficient interpolators and filter banks using multiplier blocks
3. Use of minimum-adder multiplier blocks in FIR digital filters
4. Splitting the unit delay, tools for fractional delay filter design
5. Multiple constant multiplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination
6. Optimization method for broadband modem FIR filter design using common subexpression elimination
7. Interpolation in digital modems - Part II: Implementation and performance
8. Design and properties of polynomial-based fractional delay filters
9. Efficient design of a class of multiplier-less perfect reconstruction two-channel filter banks and wavelets with prescribed output accuracy