Multiwafer vertical interconnects for three-dimensional integrated circuits

IEEE Transactions on Microwave Theory and Techniques

Volumn 54, Issue 6, 2006, Pages 2699-2705

  Lahiji, Rosa R ^a,b   Herrick, Katherine J ^a,c   Lee, Yongshik ^a,d   Margomenos, Alexandros ^a,e   Mohammadi, Saeed ^a,b   Katehi, Linda P B ^a,b  

^a IEEE   (United States)

^b PURDUE UNIVERSITY   (United States)

^c RAYTHEON COMPANY   (United States)

^d Yonsei University   (South Korea)

^e EMAG Technologies Inc   (United States)

Author keywords

Integrated circuit packaging; Microstrip line; Vertical interconnects

Indexed keywords

INTEGRATED CIRCUIT PACKAGING; MULTIWAFER VERTICAL INTERCONNECTS; RETURN LOSSES;

INSERTION LOSSES; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; MICROSTRIP LINES; SEMICONDUCTING GALLIUM ARSENIDE; WSI CIRCUITS;

OPTICAL INTERCONNECTS;

EID: 33947402291     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2006.874867     Document Type: Article

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