A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 12, 2006, Pages 1436-1440

  Li, Chin Fu ^a   Huang, Po Chiun ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

Author keywords

CMOS integrated circuit; linear in decibel variable gain amplifier (VGA)

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; BUFFER CIRCUITS; CLOSED LOOP SYSTEMS; GAIN CONTROL;

CURRENT-BUFFERED COMPENSATION; GROUP DELAY; LOW-VOLTAGE OPERATION; VARIABLE GAIN AMPLIFIER (VGA);

CMOS INTEGRATED CIRCUITS;

EID: 33947371258     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.885399     Document Type: Article

References (13)

1. T. Fujisawa, J. Hasegawa, K. Tsuchie, T. Shiozawa, T. Fujita, T. Saito, and Y. Unekawa, “A single-chip 802.11a MAC/PHY with a 32 b RISC processor, ” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 2001–2009, Nov. 2003.
2. C.-K. Wang and P.-C. Huang, “An automatic gain control architecture for SONET OC-3 VLSI, ” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 9, pp. 779–783, Sep. 1997.
3. C.-H. Wu, C.-S. Liu, and S.-I. Liu, “A 2 GHz CMOS variable-gain amplifier with 50-dB linear-in-magnitude controlled gain range for 10GBase-LX4 ethernet, ” in Proc. IEEE Int. Solid-State Circuits Conf., 2004, pp. 484–485, Session 26.8.
4. F. Carrara and G. Palmisano, “High-dynamic-range VGA with temperature compensation and linear-in-dB gain control, ” IEEE J. Solid-State Circuits, vol. 40, no. 10, pp. 2019–2024, Oct. 2005.
5. P. Orsatti, F. Piazza, and Q. Huang, “A 71-MHz CMOS IF-baseband strip for GSM, ” IEEE J. Solid-State Circuits, vol. 35, pp. 104–108, Jan. 2000.
6. J. J. F. Rijns, “CMOS low-distortion high-frequency variable gain amplifier, ” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 1029–1034, Jul. 1996.
7. ppoutput in 0.25-μm CMOS, ” in Proc. IEEE Symp. VLSI Circuits, 2001, pp. 81–82.
8. B. Calvo, S. Celma, P. A. Martinez, and M. T. Sanz, “1.8-V 100-MHz CMOS programmable gain amplifier, ” in Proc. IEEE Symp. Circuits Syst., 2006, pp. 1555–1558.
9. H. O. Elwan and M. Ismail, “Digitally programmable decibel-linear CMOS VGA for low-power mixed-signal applications, ” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 5, pp. 388–398, May 2000.
10. C.-C. Hsu and J.-T. Wu, “A highly linear 125-MHz switched resistor programmable gain amplifier, ” IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1663–1670, Oct. 2003.
11. P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed. New York: Wiley, 2001.
12. D. B. Ribner and M. A. Copeland, “Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range, ” IEEE J. Solid-State Circuits, vol. 19, no. 12, pp. 919–925, Dec. 1984.
13. R. Schaumann and M. van Valkenberg, Design of Analog Filters. Oxford, U.K.: Oxford University Press, 2001.