A design methodology for efficient application-specific on-chip interconnects

IEEE Transactions on Parallel and Distributed Systems

Volumn 17, Issue 2, 2006, Pages 174-189

  Ho, Wai Ng ^a,b   Pinkston, Timothy Mark ^a,b  

^a IEEE   (United States)

^b IEEE ^*  (United States)

Author keywords

Communication model; Irregular topology; Low contention communication; Network partitioning; On chip interconnects

Indexed keywords

COMMUNICATION MODELS; IRREGULAR TOPOLOGY; LOW CONTENTION COMMUNICATION; NETWORK PARTITIONING;

BLOCKING PROBABILITY; CHIP SCALE PACKAGES; INTERCONNECTION NETWORKS; PARALLEL PROCESSING SYSTEMS; RESOURCE ALLOCATION;

INTEGRATED CIRCUIT LAYOUT;

EID: 33947367855     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2006.15     Document Type: Article

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