A system-level framework for designing and evaluating protocol processor architectures

International Journal of Embedded Systems

Volumn 1, Issue 1-2, 2005, Pages 78-90

  Virtanen, Seppo ^a   Nurmi, Tero ^a   Paakkulainen, Jani ^a   Lilius, Johan ^b  

^a UNIVERSITY OF TURKU   (Finland)

^b ÅBO AKADEMI UNIVERSITY   (Finland)

Author keywords

component reuse; design methodology; design space exploration; design verification; system level design

Indexed keywords

EID: 33947103749     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2005.008810     Document Type: Article

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