Highly reliable 2-bit/cell nitride trapping flash memory using a novel array-nitride-sealing (ANS) ONO process

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 551-554

  Shih, Yen Hao ^a   Lee, S C ^b   Lue, H T ^a   Wu, M D ^a   Hsu, T H ^a   Lai, E K ^a   Hsieh, J Y ^b   Wu, C W ^b   Yang, L W ^b   Hsieh, Kuang Yeu ^a   Chen, K C ^b   Liu, Rich ^a   Lu, Chih Yuan ^a  

^a Emerging Central Lab   (Taiwan)

^b MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CHARGE TRAPPING; INTERFACES (MATERIALS); SILICON;

ARRAY-NITRIDE-SEALING (ANS); ELECTRON LOSS; ROBUST TUNNEL OXIDE;

FLASH MEMORY;

EID: 33847746644     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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