Source-pulsed dynamic-threshold CMOS SRAMs for fast, portable applications

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 360-363

  Bhavnagarwala, A J ^a   Kapoor, A ^b   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL TRANSISTOR; HSPICE SIMULATIONS; INDUSTRIAL PROCESSS; PORTABLE APPLICATIONS; READ CURRENT; SRAM CELL; STANDBY POWER; STATIC NOISE MARGIN;

CELLS; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

CYTOLOGY;

EID: 33847730789     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. R. W. Keyes, "The Effect of Randomness in the Distribution of Impurity Atoms on FET Threshold," App. Phys., 8, 1975, pp. 251-259.
2. T. Mizuno, J. Okamura, and A. Toriumi, "Experimental Study of Threshold Voltage Fluctuations using an 8K MOSFET Array," Symp. VLSI Tech., Jun. 1993, pp. 41-42.
3. J.D. Meindl et al, "Impact of Stochastic Dopant and Interconnect Distributions on Gigascale Integration," Proceedings of the 1997 IEEE ISSCC, February 1997, pp.232-233.
4. K. Itoh, "Low Power Memory Dsgn.," Tutorial slides, 1997 ISLPED
5. B. Bateman, "High Performance SRAM Design," Tutorial slides, ISSCC, Feb. 1998.
6. E. Seevinck, F. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE JSSC, Vol. SC-22, No. 5, Oct. 1987, pp. 748-754.
7. K.Anami et al, "Design Considerations of a Static Memory Cell," IEEE Jrnl. Of Sol. State Ckts., Vol. SC-18, No. 4, Aug 1983, pp. 414-417.
8. M. Inohara et al, "Highly Scalable and Fully Logic Compatible SRAM Cell Technology with Metal Damascene Process and W Local Interconnect," IEEE Symp. VLSI Tech., Jun. 1998, pp. 64-65.
9. D. Burger, "System-Level Implications of Processor-Memory Integration," 24th Int'l Symp. On Comp. Arch., June '97.
10. K. Itoh, "Trends in Low Power RAM Circuit Technologies," Proc. IEEE, Vol. 83, No. 4, Apr '95, pp. 524-543.
11. M. Ishida et al, "A Novel 6T-SRAM Cell Technology Designed with Rectangular Patterns Scalable beyond 0.18mm Generation and Desirable for Ultra High Speed Operation," IEDM Dig. of Tech. papers, Dec. 1998, pp. 201-204.
12. K Itoh et al, "A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-VT, Boosted Storage Node and Dynamic Load," IEEE Symp. VLSI Ckts., Jun 1996, pp. 132-133
13. H. Mizuno et al, "Driving Source Line (DSL) Cell Architecture for Sub 1-V High Speed Low Power Applications," 1995 Symp. VLSI Ckts., Jun 1995, pp. 25-26.
14. H Yamauchi, et al, "A 0.8V/100MHz/sub-5mW Operated Mega-bit SRAM Cell Architecture with Charge Recycle Offset-Source Driving (OSD) Scheme," 1996 Symp. VLSI Ckts., June 1996 pp. 126-127.