Low-power optimization by smart bit-width allocation in a systemC-based ASIC design environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 26, Issue 3, 2007, Pages 447-454

  Mallik, Arindam ^a,b   Sinha, Debjit ^a,b,c   Banerjee, Prithviraj ^a,b,d   Zhou, Hai ^a,b  

^a IEEE   (United States)

^b Northwestern University   (United States)

^c IBM MICROELECTRONICS   (United States)

^d UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Fixed point arithmetic; High level synthesis; Low power design; Quantization

Indexed keywords

FIXED-POINT ARITHMETIC; HIGH-LEVEL SYNTHESIS; LOW-POWER DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATION THEORY; EMBEDDED SYSTEMS; HEURISTIC ALGORITHMS; RESOURCE ALLOCATION;

OPTIMIZATION;

EID: 33847701654     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.888291     Document Type: Conference Paper

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