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Volumn 2005, Issue , 2005, Pages 1768-1772

A high-speed analog min-sum iterative decoder

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG MIN-SUM (MS) ITERATIVE DECODERS; CMOS TECHNOLOGY; CURRENT-MODE CIRCUITS; LDPC CODES;

EID: 33749441448     PISSN: 21578099     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISIT.2005.1523649     Document Type: Conference Paper
Times cited : (3)

References (15)
  • 3
    • 0242657937 scopus 로고    scopus 로고
    • A 13.3-Mb/s 0.35μm CMOS analog turbo decoder IC with a configurable interleaver
    • Nov.
    • V.C. Gaudet and P.G. Gulak, "A 13.3-Mb/s 0.35μm CMOS analog turbo decoder IC with a configurable interleaver," IEEE J. Solid-States Circuits, vol. 38, no. 11, pp. 2010-2015, Nov. 2003.
    • (2003) IEEE J. Solid-states Circuits , vol.38 , Issue.11 , pp. 2010-2015
    • Gaudet, V.C.1    Gulak, P.G.2
  • 9
    • 0019608335 scopus 로고
    • A recursive approach to low complexity codes
    • Sept.
    • R. M. Tanner, "A recursive approach to low complexity codes," IEEE Trans. Inform. Theory, vol. IT-27, pp. 533-547, Sept. 1981.
    • (1981) IEEE Trans. Inform. Theory , vol.IT-27 , pp. 533-547
    • Tanner, R.M.1
  • 12
    • 0029771861 scopus 로고    scopus 로고
    • CMOS current mirrors with reduced input and output voltage requirements
    • Jan.
    • V. I. Prodanov and M. M. Green "CMOS current mirrors with reduced input and output voltage requirements," Electronic. Lett., vol. 32, no. 2, pp. 104-105, Jan. 1996.
    • (1996) Electronic. Lett. , vol.32 , Issue.2 , pp. 104-105
    • Prodanov, V.I.1    Green, M.M.2
  • 13
    • 19644377874 scopus 로고    scopus 로고
    • On implementation of min-sum algorithm and its modifications for decoding LDPC codes
    • April
    • J. Zhao, F. Zarkeshvari, and A. H. Banihashemi, "On implementation of min-sum algorithm and its modifications for decoding LDPC codes," IEEE Trans. Comm., vol. 53, no. 4, pp. 549-554, April 2005.
    • (2005) IEEE Trans. Comm. , vol.53 , Issue.4 , pp. 549-554
    • Zhao, J.1    Zarkeshvari, F.2    Banihashemi, A.H.3
  • 15
    • 33847170601 scopus 로고    scopus 로고
    • An 80-Mb/s 0.18-μm CMOS analog min-sum iterative decoder for a (32,8,10) LDPC code
    • accepted for presentation, San Jose, California
    • S. Hemati, A. H. Banihashemi, and C. Plett, "An 80-Mb/s 0.18-μm CMOS Analog Min-Sum Iterative Decoder for a (32,8,10) LDPC Code," accepted for presentation in IEEE Custom Integrated Circuit Conference, San Jose, California, 2005.
    • (2005) IEEE Custom Integrated Circuit Conference
    • Hemati, S.1    Banihashemi, A.H.2    Plett, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.