A novel strain method for enhancement of 90-nm node and beyond FUSI-gated CMOS performance

IEEE Electron Device Letters

Volumn 28, Issue 2, 2007, Pages 111-113

  Lin, Chien Ting ^a   Fang, Yean Kuen ^a   Yeh, Wen Kuan ^b   Lee, Tung Hsing ^a   Chen, Ming Shing ^a   Lai, Chieh Ming ^a   Hsu, Che Hua ^c   Chen, Liang Wei ^c   Cheng, Li Wei ^c   Ma, Mike ^c  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL UNIVERSITY OF KAOHSIUNG   (Taiwan)

^c UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Contact etch stop layer (CESL); Fully silicided (FUSI); Phase transfer; Strain engineering; Tensile stress

Indexed keywords

ETCHING; RAPID THERMAL PROCESSING; TENSILE STRESS;

CONTACT ETCH STOP LAYER; FULLY SILICIDED; PHASE TRANSFER;

CMOS INTEGRATED CIRCUITS;

EID: 33847374269     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.889633     Document Type: Article

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