-
1
-
-
0036932380
-
"Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates"
-
W. P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, and M.-R. Lin, "Transistors with dual work function metal gate by single full silicidation (FUSI) of polysilicon gates," in IEDM Tech. Dig., 2002, pp. 367-370.
-
(2002)
IEDM Tech. Dig.
, pp. 367-370
-
-
Maszara, W.P.1
Krivokapic, Z.2
King, P.3
Goo, J.-S.4
Lin, M.-R.5
-
2
-
-
4544294546
-
"Dual workfunction fully silicided metal gates"
-
C. Cabral, Jr., J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy, "Dual workfunction fully silicided metal gates," in VLSI Symp. Tech. Dig., 2004, pp. 184-185.
-
(2004)
VLSI Symp. Tech. Dig.
, pp. 184-185
-
-
Cabral Jr., C.1
Kedzierski, J.2
Linder, B.3
Zafar, S.4
Narayanan, V.5
Fang, S.6
Steegen, A.7
Kozlowski, P.8
Carruthers, R.9
Jammy, R.10
-
3
-
-
4544335208
-
2 based high-κ gate dielectrics as a candidate for low power applications"
-
2 based high-κ gate dielectrics as a candidate for low power applications," in VLSI Symp. Tech. Dig., 2004, pp. 190-191.
-
(2004)
VLSI Symp. Tech. Dig.
, pp. 190-191
-
-
Anil, K.G.1
Veloso, A.2
Kubicek, S.3
Schram, T.4
Augendre, E.5
de Marneffe, J.-F.6
Devriendt, K.7
Lauwers, A.8
Brus, S.9
Henson, K.10
Biesemans, S.11
-
4
-
-
21644466972
-
"Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled fullsilicidation (PC-FUSI) technique for 45 nm-node LSTP and LOP devices"
-
K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T. Yoshihara, H. Watanabe, T. Tatsumi, and Y. Mochizuki, "Dual workfunction Ni-silicide/HfSiON gate stacks by phase-controlled fullsilicidation (PC-FUSI) technique for 45 nm-node LSTP and LOP devices," in IEDM Tech. Dig., 2004, pp. 91-94.
-
(2004)
IEDM Tech. Dig.
, pp. 91-94
-
-
Takahashi, K.1
Manabe, K.2
Ikarashi, T.3
Ikarashi, N.4
Hase, T.5
Yoshihara, T.6
Watanabe, H.7
Tatsumi, T.8
Mochizuki, Y.9
-
5
-
-
31544465605
-
"Scalability of Ni FUSI gate processes: Phase and Vt control to 30 nm gate lengths"
-
J. A. Kittl, A. Veloso, A. Lauwers, K. G. Anil, C. Demeurisse, S. Kubicek, M. Niwa, M. J. H. van Dal, O. Richard, M. A. Pawlak, M. Jurczak, C. Vrancken, T. Chiarella, S. Brus, K. Maex, and S. Biesemans, "Scalability of Ni FUSI gate processes: Phase and Vt control to 30 nm gate lengths," in VLSI Symp. Tech. Dig., 2005, pp. 72-73.
-
(2005)
VLSI Symp. Tech. Dig.
, pp. 72-73
-
-
Kittl, J.A.1
Veloso, A.2
Lauwers, A.3
Anil, K.G.4
Demeurisse, C.5
Kubicek, S.6
Niwa, M.7
van Dal, M.J.H.8
Richard, O.9
Pawlak, M.A.10
Jurczak, M.11
Vrancken, C.12
Chiarella, T.13
Brus, S.14
Maex, K.15
Biesemans, S.16
-
6
-
-
33645465482
-
3Si fully silicided gates"
-
Jan
-
3Si fully silicided gates," IEEE Electron Device Lett., vol. 27, no. 1, pp. 34-36, Jan. 2006.
-
(2006)
IEEE Electron Device Lett.
, vol.27
, Issue.1
, pp. 34-36
-
-
Kittl, J.A.1
Pawlak, M.A.2
Lauwers, A.3
Demeurisse, C.4
Opsomer, K.5
Anil, K.G.6
Vrancken, C.7
van Dal, M.J.H.8
Veloso, A.9
Kubicek, S.10
Absil, P.11
Maex, K.12
Biesemans, S.13
|