Design synthesis and performance measurement of pipelined flash ADC for SoC applications

Conference Record - IEEE Instrumentation and Measurement Technology Conference

Volumn 1, Issue , 2005, Pages 19-24

  Wang, Mingzhen ^a   Chen, Chien In Henry ^a  

^a Wright State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PERFORMANCE MEASUREMENT; SAMPLING RATE; SOC APPLICATIONS;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; PROBLEM SOLVING;

ANALOG TO DIGITAL CONVERSION;

EID: 33847183195     PISSN: 10915281     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMTC.2002.1006809     Document Type: Conference Paper

References (9)

1. X. Jiang, Z. Wang and M.F. Chang, "A 2GS/S 6-b ADC in 0.18 μm CMOS," IEEE Intl. Solid-State Circuits Conference, vol. 1, pp. 9-13, Feb. 2003
2. M. Choi and A. Abidi, "A 6-b 1.3 Gsamples/s A/D converter in 0.35 μm CMOS," IEEE Journal of Solid-State Circuits, Vol. 36, pp. 1847-1858, Dec. 2001.
3. P.C.S. Scholtens and M. Bertregt, "A 6-bit 1.6 Gsamples/s Flash ADC in 0.18 μm CMOS using Averaging Termination," IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, December 2002.
4. J.-E. Eklund, "Robust ADC concept for integrated CMOS systems," IEE Third International Conference on Advanced A/D and D/A Conversion Techniques and their Applications, pp. 126-129, July 1999.
5. J. Yoo, K. Choi, D. Lee. "Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter," Journal of Analog Integrated Circuits and Signal Processing, 35(2-3), pp. 179-187, 2003.
6. J. Yoo, K. Choi, and J. Ghaznavi, "Quantum voltage comparator for 0.07 μm flash A/D converters," IEEE Computer Society Annual Symposium on VLSI, pp. 20-21, Feb. 2003
7. D. Lee, J. Yoo, K. Choi and J. Ghaznavi, "Fat-tree encoder design for ultra-high speed flash analog-to-digital converters," IEEE Midwest Symposium on Circuits and Systems, 2002.
8. F. Lai and W. Hwang, "Design and implementaion of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems," IEEE Journal of Solid-State Circuits, vol. 32, April 1997.
9. J. Segura, J. L. Rossello, J.Morra, and H. Sigg. "A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits," IEEE Journal of Solid-State Circuits, 33(8), pp. 1262-1265, August 1998.