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Volumn 33, Issue 8, 1998, Pages 1262-1265

A variable threshold voltage inverter for CMOS programmable logic circuits

Author keywords

Buffer circuits; Integrated circuit design

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; DESIGN; FABRICATION; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

EID: 0032141701     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.705367     Document Type: Article
Times cited : (39)

References (8)
  • 2
    • 0021477994 scopus 로고
    • Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits
    • H. Veendrick, "Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits," IEEE J. Solid-State Circuits, vol. 19, pp. 468-473, 1984.
    • (1984) IEEE J. Solid-State Circuits , vol.19 , pp. 468-473
    • Veendrick, H.1
  • 3
    • 0028499207 scopus 로고
    • Energy control and accurate delay estimation in the design of CMOS buffers
    • Sept.
    • S. Ma and P. Franzon, "Energy control and accurate delay estimation in the design of CMOS buffers," IEEE J. Solid-State Circuits, vol. 29, pp. 1150-1153, Sept. 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 1150-1153
    • Ma, S.1    Franzon, P.2
  • 4
    • 0029379529 scopus 로고
    • Short-circuit power driven gate sizing technique for reducing power dissipation
    • Sept.
    • U. Ko and P. T. Balsara, "Short-circuit power driven gate sizing technique for reducing power dissipation," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 3, pp. 450-455, Sept. 1995.
    • (1995) IEEE Trans. Very Large Scale Integration (VLSI) Syst. , vol.3 , pp. 450-455
    • Ko, U.1    Balsara, P.T.2
  • 5
    • 0029304718 scopus 로고
    • A static power saving TTL-to-CMOS input buffer
    • May
    • C. Yoo, M. K. Kim, and W. Kim, "A static power saving TTL-to-CMOS input buffer," IEEE J. Solid-State Circuits, vol. 30, pp. 616-620, May 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , pp. 616-620
    • Yoo, C.1    Kim, M.K.2    Kim, W.3
  • 8
    • 0026900034 scopus 로고
    • A unified theory for mixed CMOS/BiCMOS buffer optimization
    • July
    • T. Sakurai, "A unified theory for mixed CMOS/BiCMOS buffer optimization," IEEE J. Solid-State Circuits, vol. 27, pp. 1014-1019, July 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , pp. 1014-1019
    • Sakurai, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.