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Volumn 2005, Issue , 2005, Pages 111-119

Testability features of the first-generation cell processor

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS MACHINERY; LOGIC DESIGN; SYNCHRONOUS MACHINERY;

EID: 33847093317     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1583967     Document Type: Conference Paper
Times cited : (26)

References (11)
  • 1
    • 27344435504 scopus 로고    scopus 로고
    • The Design and Implementation of a First-Generation CELL Processor
    • Feb
    • D. Pham, et al, "The Design and Implementation of a First-Generation CELL Processor," IEEE International Solid State Circuits Symposium, Feb 2005.
    • (2005) IEEE International Solid State Circuits Symposium
    • Pham, D.1
  • 2
    • 33847125984 scopus 로고    scopus 로고
    • Proceedings of the IEEE Computer Society International Computer Conference, 1993
    • Paap, Silha, PowerPC: A Performance Architecture", Proceedings of the IEEE Computer Society International Computer Conference, 1993.
    • Paap1    Silha2    Power, P.C.3
  • 6
    • 33847095337 scopus 로고    scopus 로고
    • U.S. Patent 4293919, Level Sensitive Scan Design System, 1981
    • Dasgupta, et al, U.S. Patent 4293919, "Level Sensitive Scan Design System", 1981.
    • Dasgupta1
  • 8
    • 0036734162 scopus 로고    scopus 로고
    • Extending OPMISR beyond 10x Scan Test Efficiency
    • C. Barnhart, et al, "Extending OPMISR beyond 10x Scan Test Efficiency", IEEE Design and Test of Computers, 2001, pp. 65-72.
    • (2001) IEEE Design and Test of Computers , pp. 65-72
    • Barnhart, C.1
  • 9
    • 84943549146 scopus 로고    scopus 로고
    • Analysis and design of optimal combinational compactors[logic test]
    • P. Wohl, L. Huisman, "Analysis and design of optimal combinational compactors[logic test]", VLSI Test Symposium", 2003.
    • (2003) VLSI Test Symposium
    • Wohl, P.1    Huisman, L.2
  • 10
    • 33847146566 scopus 로고
    • MC68HC11 Reference Manual
    • Motorola, "MC68HC11 Reference Manual", Prentice Hall, 1989.
    • (1989) Prentice Hall
    • Motorola1
  • 11
    • 33847104032 scopus 로고    scopus 로고
    • Standard Test Access Port and Boundary Scan Architecture, IEEE Standard 1149.1-2001
    • IEEE 1149.1
    • IEEE 1149.1, "Standard Test Access Port and Boundary Scan Architecture", IEEE Standard 1149.1-2001.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.