Wafer-level stress in combination with process induced stress for optimum performance enhancement

ECS Transactions

Volumn 3, Issue 7, 2006, Pages 399-410

  Cayrefourcq, I ^a   Boussagol, A ^a   Celler, G ^a  

^a PARC TECHNOLOGIQUE DES FONTAINES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; MOS DEVICES; SILICON WAFERS; STRAIN MEASUREMENT;

MECHANICAL MODELING; SCALABILITY; WAFER-LEVEL STRESSES;

STRESS ANALYSIS;

EID: 33846960203     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2355837     Document Type: Conference Paper

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