Offset-trimming bit-line sensing scheme for Gigabit-scale DRAM's

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 7, 1996, Pages 1025-1028

  Suh, Jung Won ^a,b,c   Rho, Kwang Myoung ^a,b,c,d   Park, Chan Kwang ^a,b,d,e   Koh, Yo Hwan ^a,b,d,e,f,g  

^a IEEE

^b Hynix Semiconductor Inc   (South Korea)

^c Seoul National University   (South Korea)

^d Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^e Sogang University   (South Korea)

^f Memory R and D Division

^g Korean Inst Telematics Electronics

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINE PRECHARGE VOLTAGE; DEEP SUBMICRON TRANSISTORS; DYNAMIC RANDOM ACCESS MEMORY; ELECTRICAL MISMATCH; ELECTRICAL PARAMETER VARIATION; OFFSET TRIMMING BIT LINE SENSING SCHEME; OFFSET VOLTAGE DEPENDENCE;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIFFERENTIAL AMPLIFIERS; ELECTRIC INVERTERS; FEEDBACK; MATHEMATICAL MODELS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS;

RANDOM ACCESS STORAGE;

EID: 0030189807     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.508216     Document Type: Article

References (8)

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