On the difference between thermal cycling and thermal shock testing for board level reliability of soldered interconnections

Microelectronics Reliability

Volumn 47, Issue 2-3, 2007, Pages 444-449

  de Vries, J W C ^a   Jansen, M Y ^a   van Driel, W D ^b,c  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b NXP SEMICONDUCTORS   (Netherlands)

^c DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; TEMPERATURE MEASUREMENT; THERMAL CYCLING;

BALL GRID ARRAY PACKAGE; BOARD LEVEL RELIABILITY; SOLDERED INTERCONNECTIONS; THERMAL SHOCK TESTING;

INTERCONNECTION NETWORKS;

EID: 33846568998     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2006.05.009     Document Type: Article

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