Random switching logic: A new countermeasure against DPA and second-order DPA at the logic level

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E90-A, Issue 1, 2007, Pages 160-168

  Suzuki, Daisuke ^a   Saeki, Minoru ^a   Ichikawa, Tetsuya ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

CMOS logic circuit; Differential power analysis; Hardware countermeasure; Second order DPA random switching logic; Side channel attacks

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIFFERENTIAL EQUATIONS; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC CIRCUITS; RANDOM PROCESSES; SWITCHING FUNCTIONS;

CMOS LOGIC CIRCUIT; DIFFERENTIAL POWER ANALYSIS; HARDWARE COUNTERMEASURE; SECOND ORDER DPA RANDOM SWITCHING LOGIC; SIDE CHANNEL ATTACKS;

FORMAL LOGIC;

EID: 33846526735     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e90-a.1.160     Document Type: Conference Paper

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