DPA leakage models for CMOS logic circuits

Lecture Notes in Computer Science

Volumn 3659, Issue , 2005, Pages 366-382

  Suzuki, Daisuke ^a   Saeki, Minoru ^a   Ichikawa, Tetsuya ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS; PROBABILITY; SECURITY OF DATA;

HARDWARE COUNTERMEASURES; LEAKAGE MODELS; POWER ANALYSIS; TRANSITION PROBABILITY;

LOGIC CIRCUITS;

EID: 27244445509     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11545262_27     Document Type: Conference Paper

References (21)

1. P. Kocher, J. Jaffe and B. Jun, "Differential Power Analysis," Crypto'99, LNCS 1666, pp. 388-397, Springer-Verlag, 1999.
2. J.-S. Coron, "Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems," CHES'99, LNCS 1717, Springer-Verlag, pp. 292-302, 1999.
3. M. Akkar and C. Giraud, "An Implementation of DES and AES, Secure against Some Attacks," CHES 2001, LNCS 2162, pp. 309-318, Springer-Verlag, 2001.
4. K. Tiri, M. Akmal and I. Verbauwhede, "A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on SmartCards," Proc. of 28th European Solid-State Circuits Conference, pp.403-406, 2002.
5. K. Tiri and I. Verbauwhede, "Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology," CHES 2003, LNCS 2779, p.125-136, Springer-Verlag, 2003.
6. K. Tiri and I. Verbauwhede, "A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation," In Proc. of Design Automation and Test in Europe Conference, pp. 246-251, 2004.
7. E. Trichina, "Combinational Logic Design for AES SubByte Transformation on Masked Data," Cryptology ePrint Archive, 2003/236, 2003.
8. S. Chari, C.S. Jutla, J.R. Rao and P. Rohatgi, "Towards Sound Approaches to Counteract Power Analysis Attacks," Crypto'99, LNCS 1666, pp. 398-412, Springer-Verlag, 1999.
9. C. Clavier, J.-S. Coron and N. Dabbous, "Differential Power Analysis in the Presence of Hardware Countermeasures," CHES 2000, LNCS 1965, pp. 252-263, Springer-Verlag, 2000.
10. R. Bevan and E. Knudsen, "Ways to Enhance Differential Power Analysis," ICISC 2002, LNCS 2587, pp. 327-342, Springer-Verlag, 2003.
11. D. Suzuki, M.Saeki and T.Ichikawa, "Random Switching Logic: A Countermeasure against DPA based on Transition Probability," Cryptology ePrint Archive, Report 2004/346, 2004.
12. T.S. Messerges, "Using Second-Order Power Analysis to Attack DPA Resistant Software," CHES 2000, LNCS 1965, pp. 238-251, Springer-Verlag, 2000.
13. J. Waddle and D. Wagner, "Towards Efficient Second-Order Power Analysis," CHES 2004, LNCS 3156, pp. 1-15, Springer-Verlag, 2004.
14. M. Saeki, D. Suzuki and T. Ichikawa, "Construction of DPA Leakage Model and Evaluation by Logic Simulation," ISEC2004-57, IEICE, July 2004 (in Japanese).
15. M. Akkar, R. Bevan, P. Dischamp and D. Moyart, "Power Analysis, What Is Now Posible...," Asiacrypto 2000, LNCS 1976, pp. 489-502, Springer-Verlag, 2000.
16. A.P. Chandrakasan, S. Sheng and R.W. Brodersen, "Low Power Digital CMOS Design," IEEE Journal of Solid State Circuits, Vol.27, N0.4. pp. 473-484, 1992.
17. Philips Electronics NV, "DATA CARRIER WITH OBSCURED POWER CONSUMPTION," Patent, WO00/026746.
18. H. Shimizu, "A Countermeasure against Side Channel Attack using Mask Logic Elements," ISEC2004-69, IEICE, September 2004 (in Japanese).
19. J. Blömer, J.G. Merchan and V. Krummel, "Provably Secure Masking of AES," Cryptology ePrint Archive, Report 2004/101, 2004.
20. T. Ichikawa, D. Suzuki and M. Saeki, "An Attack on Cryptographic Hardware Design with Masking Method," ISEC2004-58, IEICE, July 2004 (in Japanese).
21. S. Mangard, T. Popp, and B. M. Gammel," Side-Channel Leakage of Masked CMOS Gates", CT-RSA 2005, LNCS 3376, pp. 361-365, Springer-Verlag, 2005