Transactional memory

Synthesis Lectures on Computer Architecture

Volumn 2, Issue , 2007, Pages 1-220

  Larus, James R ^a   Rajwar, Ravi ^b  

^a MICROSOFT   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Cache coherence; Compilers; Computer architecture; Computer hardware; Concurrent programming; Parallel programming; Programming languages; Synchronization; Transactional memory; Wait free data structures

Indexed keywords

BUFFER STORAGE; COMPUTATION THEORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING; COMPUTER PROGRAMMING LANGUAGES; CURRENT LIMITING REACTORS; DATA STRUCTURES; MATHEMATICAL MODELS; PROGRAM COMPILERS; SYNCHRONIZATION;

CACHE COHERENCE; CONCURRENT PROGRAMMING; MULTICORE PROCESSORS; PARALLEL PROGRAMMING; PARALLEL PROGRAMS; TRANSACTIONAL MEMORY; WAIT-FREE DATA STRUCTURES;

STORAGE ALLOCATION (COMPUTER);

EID: 33846500798     PISSN: 19353235     EISSN: 19353243     Source Type: Book Series    
DOI: 10.2200/S00070ED1V01Y200611CAC002     Document Type: Article

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