High performance 65nm SOI transistors using laser spike annealing

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn 2006-January, Issue , 2006, Pages 347-350

  Yamashita, Tenko ^a   Fisher, Philip A ^b   Gluschenkov, Oleg ^c   Kimura, Hideki ^a   Ramachandran, Ravikumar ^c   Mocuta, Anda C ^c   Kluth, Jon ^b   Kawamura, Takahiro ^a   Onishi, Katsunori ^c   Fried, David ^c   Narasimha, Shreesh ^c   Brown, David ^b   Jain, Sameer ^c   Miyamoto, Koji ^d   Freeman, Greg ^c   Deshpande, Sadanand V ^c   Luning, Scott ^b   Huang, Shih Fen ^c   Pellerin, John ^b   Kuroda, Hideaki ^a  

^a SONY CORPORATION   (Japan)

^b ADVANCED MICRO DEVICES   (United States)

^c IBM JAPAN LTD   (Japan)

^d TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DELAY CIRCUITS; OSCILLATORS (ELECTRONIC); SOLID STATE DEVICES;

DELAY IMPROVEMENTS; DRIVE CURRENT ENHANCEMENT; OVERLAP CAPACITANCE; PRODUCT PERFORMANCE; SELF-HEATING EFFECT; SIMULTANEOUS OPTIMIZATION; STATISTICAL DISTRIBUTION; TRANSISTOR PERFORMANCE;

SILICON ON INSULATOR TECHNOLOGY;

EID: 84957878143     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/essder.2006.307709     Document Type: Conference Paper

References (4)

1. K. Adachi et al., Intl. Junction Tech. Workshop 2002.
2. S.K.H.Fung et al., Proc. IEEE VLSI Tech. Symp. 2004.
3. A.Shima et al., Proc. IEEE VLSI Tech. Symp. 2005.
4. A. Pouydebasque et al., IEDM Tech. Dig. 20005