4.0GHz 0.18.μm CMOS PLL based on an interpolative oscillator

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn 2005, Issue , 2005, Pages 100-103

  Gebara, Fadi H ^a   Schaub, Jeremy D ^b   Drake, Alan J ^b   Nowka, Kevin J ^b   Brown, Richard B ^c  

^a University of Michigan   (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

^c Department of Electrical and Computer Engineering   (United States)

Author keywords

CMOS; Interpolation; Oscillator; PLL

Indexed keywords

CLOCKING; FREQUENCY PERFORMANCE; INTERPOLATIVE OSCILLATORS; OUTPUT SIGNALS;

DIGITAL CIRCUITS; INTERPOLATION; MICROPROCESSOR CHIPS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS;

CMOS INTEGRATED CIRCUITS;

EID: 33745155097     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2005.1469343     Document Type: Conference Paper

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