A 20GB/s 256Mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages 470-471

  Kim, Kyu Hyoun ^a   Sohn, Young Soo ^a   Kim, Chan Kyoung ^a   Lee, Dong Jin ^a   Byun, Gyung Su ^a   Lee, Hoon ^a   Lee, Jae Hyoung ^a   Sunwoo, Jung ^a   Choi, Jung Hwan ^a   Chai, Jun Wan ^a   Kim, Changhyun ^a   Cho, Soo In ^a  

^a Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144448840     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. S. Sidiropoulos et al., "Adaptive Bandwidth DLLs and PLLs Using Regulated Supply CMOS Buffer," Symp. VLSI Circuits, pp. 124-127, June, 2000.
2. K-Y. Chang et al., "A 0,4-4Gb/s CMOS Quad Tranceiver Cell Using on-Chip Regulated Dual-Loop PLLs," Symp. VLSI Circuits, pp. 88-91, June, 2002.
3. Y-S. Sohn et al., "A512Mb, 3.2Gbps/pin Packet-Based DRAM with Cost-Efficient Clock Generation and Distribution Scheme," Symp. VLSI Circuits, pp. 36-37, June, 2004.