Self-dual parity checking - a new method for on-line testing

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 162-168

  Saposhnikov, Vl V ^a   Dmitriev, A ^a   Goessel, M ^a   Saposhnikov, V V ^a  

^a EMPEROR ALEXANDER I ST PETERSBURG STATE TRANSPORT UNIVERSITY   (Russian Federation)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMBINATORIAL CIRCUITS; ERROR DETECTION; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; ONLINE SYSTEMS; OPTIMIZATION;

BENCHMARK CIRCUITS; FAULT COVERAGE; MODULO 2 SUM; ONLINE TESTING; OPTIMAL SELF DUAL COMPLEMENT; PARITY CHECKING FUNCTION; SELF DUAL PARITY CHECKING;

AUTOMATIC TESTING;

EID: 0029721858     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)