Scaling rules and parameter tuning procedure for analog design reuse in technology migration

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2004, Pages

  Savio, A ^a   Colalongo, L ^a   Kavacs Vajna Zs M ^a   Quarantelli, M ^b  

^a UNIVERSITY OF BRESCIA   (Italy)

^b PDF Solutions Italia   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC POTENTIAL; GAIN CONTROL; MATHEMATICAL MODELS; OPTIMIZATION; SCHEMATIC DIAGRAMS; SIGNAL TO NOISE RATIO;

ANALOG CIRCUITS; CHANNEL LENGTH; SYSTEM ON CHIP (SOC); VOLTAGE SUPPLY;

MOSFET DEVICES;

EID: 4344630754     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. C. Galup-Montoro and M. C. Schneider, "Resizing Rules for the Reuse of MOS Analog Designs," in Proceedings SBCCI 2000: XIII Symposium on Integrated Circuits and Systems Design, Manaos, Brazil, September 2000, pp. 89-93.
2. C. Galup-Montoro, M.C. Schneider, R. M. Coitinho, "Resizing Rules for MOS Analog-Design Reuse," IEEE Design & Test of Computers, pp. 50-58, March-April 2002.
3. S. Funaba, A. Kitagawa, T. Tsukada, G. Yokomizo, "A Fast and Accurate Method of Redesigning Analog Subcircuits for Technology Scaling," Analog Integrated Circuits and Signal Processing, vol. 25, pp. 299-307, 2000.
4. http://www.neolinear.com.
5. R. Acosta, F. Silveira, P. Aguirre, "Experiences on Analog Circuit Technology Migration and Reuse," in Proceedings XV Symposium on Integrated Circuits and Systems Design, Porto Alegre, Brazil, September 2002, pp. 169-174.
6. A. I. A. Cunha, M. C. Schneider, C. Galup-Montoro, "An MOS Transistor Model for Analog Circuit Design," IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1510-1519, October 1998.
7. W. H. Press, S. A. Teukolsky, W. T. Vetterling, B. P. Flannery, Numerical Recipes in C, Cambridge University Press, second edition, 2002.