Resizing rules for the reuse of MOS analog designs

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 89-93

  Galup Montoro, C ^a   Schneider, M C ^a  

^a FEDERAL UNIVERSITY OF SANTA CATARINA   (Brazil)

Author keywords

Analog circuits; CMOS technology; Digital circuits; Electronic mail; Equations; Intellectual property; MOSFET circuits; System on a chip; Time to market; Voltage

Indexed keywords

ANALOG CIRCUITS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC POTENTIAL; ELECTRONIC MAIL; INTEGRATED CIRCUITS; INTELLECTUAL PROPERTY; SYSTEM-ON-CHIP; SYSTEMS ANALYSIS;

CMOS TECHNOLOGY; EQUATIONS; MOSFET CIRCUITS; SYSTEM ON A CHIP; TIME TO MARKET;

MOSFET DEVICES;

EID: 4344576949     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876013     Document Type: Conference Paper

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