A 12.5-Mb/s to 2.7-Gb/s Continuous-Rate CDR with Automatic Frequency Acquisition and Data-Rate Readback

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 12, 2005, Pages 2713-2724

  Dalton, Declan ^a,b   Chai, Kwet ^a,c   Evans, Eric ^a,d   Ferriss, Mark ^a,e   Hitchcox, Dave ^a,d   Murray, Paul ^a,f   Selvanayagam, Sivanendra ^a,d   Shepherd, Paul ^a,d   Devito, Lawrence ^a,d,g  

^a IEEE

^b ANALOG DEVICES   (Ireland)

^c TEXAS INSTRUMENTS   (United States)

^d Analog Devices Inc UK   (United Kingdom)

^e UNIVERSITY OF MICHIGAN   (United States)

^f Phyworks Ltd   (United Kingdom)

^g ANALOG DEVICES INC   (United States)

Author keywords

Clock and data recovery (cdr); Delay locked loop (dll); Frequency locked loop (fll); Phase locked loop (pll)

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; ELECTRONICS PACKAGING; FREQUENCIES; JITTER;

CLOCK AND DATA RECOVERY (CDR); DATA RATE; DELAY-LOCKED LOOPS (DLL); FREQUENCY-LOCKED LOOPS (FLL);

CLOCKS;

EID: 29044436276     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.856577     Document Type: Conference Paper

References (6)

1. D. Dalton et al., "A 12.5 Mb/s to 2.7 Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 2005, pp. 230-231.
2. T. Lee and J. Bulzacchelli, "A 155-MHz clock recovery delay- and phase-locked loop," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1736-1746, Dec. 1992.
3. D. Messerschmitt, "Frequency detectors for PLL acquisition in timing and carrier recovery," IEEE Trans. Commun., vol. CMO-27, no. 9, pp. 1288-1295, Sep. 1979.
4. L. DeVito et al., "A 52 MHz and 155 MHz clock recovery PLL," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 1991, pp. 142-143.
5. L. DeVito, "A versatile clock recovery architecture and monolithic implementation," in Monolithic Phase-Locked Loops and Clock Recovery Circuits, B. Razavi, Ed. Pistacaway, NJ: IEEE Press, 1996, pp. 405-420.
6. S. Paik, "The design and implementation of a new wide range frequency detector," Mass. Inst. of Technol., Cambridge, MA, MEEE Report, Jul. 1999.