A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2921-2929

  Kromer, Christian ^a,b   Sialm, Gion ^b   Menolfi, Christian ^a,c   Schmatz, Martin ^a,c   Ellinger, Frank ^a,b,d   Jäckel, Heinz ^a,b  

^a IEEE   (Switzerland)

^b ETH ZURICH   (Switzerland)

^c IBM RESEARCH ZURICH   (Switzerland)

^d DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Bang bang CDR; Clock and data recovery (CDR); CMOS; Current mode logic (CML); Data communication; High speed integrated circuits; Phase locked loops (PLL); Synchronization

Indexed keywords

BANG BANG (BB); CLOCK AND DATA RECOVERY (CDR); CURRENT MODE LOGIC (CML); DIGITAL LOOP FILTER; PHASE INTERPOLATOR;

DATA COMMUNICATION EQUIPMENT; DATA TRANSFER; JITTER; LIMITERS; LOOP ANTENNAS; OPTICAL INTERCONNECTS; OPTICAL LINKS; PHASE LOCKED LOOPS;

CMOS INTEGRATED CIRCUITS;

EID: 33845614827     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884389     Document Type: Conference Paper

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