A 2.5-Gb/s multi-rate 0.25-μm CMOS clock and data recovery circuit utilizing a hybrid analog/digital loop filter and all-digital referenceless frequency acquisition

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2930-2942

  Perrott, Michael H ^b,c   Huang, Yunteng ^a,b   Baird, Rex T ^b,d,e   Garlepp, Bruno W ^a,b,f   Pastorello, Douglas ^a,g   King, Eric T ^a,g,h   Yu, Qicheng ^g   Kasha, Dan B ^b   Steiner, Philip ^g   Zhang, Ligang ^b   Hein, Jerrell ^b   Del Signore, Bruce ^g  

^a IEEE

^b SILICON LABORATORIES   (United States)

^c MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^d Cascade Technology LLC   (United States)

^e MONTANA STATE UNIVERSITY   (United States)

^f RAMBUS INC   (United States)

^g Silicon Laboratories   (United States)

^h Avnera Corporation   (United States)

Author keywords

Analog to digital; Bit error rate (BER); Clock and data recovery (CDR); Frequency acquisition; Hybrid loop filter; Integrated loop filter; Mixed signal; Multi rate; Phase locked loop (PLL); Phase to digital; Referenceless; Sigma Delta; SONET

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DELTA SIGMA MODULATION; OPTICAL FILTERS; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

CLOCK AND DATA RECOVERY (CDR); FREQUENCY ACQUISITION; HYBRID LOOP FILTER; INTEGRATED LOOP FILTER; MULTI RATE CLOCK; PHASE TO DIGITAL;

LOOP ANTENNAS;

EID: 33845604406     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884391     Document Type: Conference Paper

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