Simulation and experimental analysis for a ball stitch on bump wire bonding process above a laminate substrate

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1918-1923

  Liu, Yong ^a   Allen, Howard ^a   Luk, Timwah ^a   Irving, Scott ^a  

^a FAIRCHILD SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BALL STITCH ON BUMP (BSOB); ULTRASONIC POWER; WIRE BONDING;

COMPUTER SIMULATION; ELECTRIC WIRE; ENCAPSULATION; TRANSIENTS; ULTRASONICS;

LAMINATES;

EID: 33845588775     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645923     Document Type: Conference Paper

References (6)

1. Ikeda T., Miyazaki, N., Kudo, K. et al, " Failure Estimation of Semiconductor Chip During Wire Bonding Process," ASME J. of Electronic Packaging, vol.121, 1999, pp85-91
2. Takahashi,Y. and Inoue, M., "Numerical study of wire bonding-Analysis of interfacial deformation between wire and pad," ASME J. of Electronic Packaging, vol.121, 2002, pp27-36
3. Gillotti, G. and Cathcart, R., "Optimizing wire bonding processes for maximum factory portability", SEMICON West 2002 SEMI Tecgnology Symposium: International Electronics Manfacturing Technology Symposium, 2002.
4. Liu, Y., Irving, S., and Luk, T., " Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active (BPOA) Stress Analysis", Proceedings of 54 th Electronic Components and Technology Conference, Las Vegas, Nevada, June 2004, pp 383-391.
5. Harman, G., and Johnson, C., "Wire Bonding to Advanced Copper, Low-K Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations", IEEE Trans on Components and Packaging Technologies, Vol.25, 2002, pp.677-683.
6. Degryse, D., Vandevelde, B. and Beyne, E., " FEM Study of Deformation and Stresses in Copper Wire Bonds on Cu Low k Structures During Processing", Proceedings of 54 th Electronic Components and Technology Conference, Las Vegas, Nevada, June 2004, pp.