Failure estimation of semiconductor chip during wire bonding process

Journal of Electronic Packaging, Transactions of the ASME

Volumn 121, Issue 2, 1999, Pages 85-91

  Ikeda, T ^a   Miyazaki, N ^a   Kudo, K ^a   Arita, K ^b   Yakiyama, H ^b  

^a KYUSHU UNIVERSITY   (Japan)

^b Kyushu Matsushita Electric Co   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELASTOPLASTICITY; FAILURE ANALYSIS; MICROPROCESSOR CHIPS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MANUFACTURE; STRESS CONCENTRATION; VIBRATIONS (MECHANICAL);

FAILURE ESTIMATION; WIRE BONDING;

ELECTRONICS PACKAGING;

EID: 0032633863     PISSN: 10437398     EISSN: 15289044     Source Type: Journal    
DOI: 10.1115/1.2792672     Document Type: Article

References (8)

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