Through wafer copper via for silicon based SiP application

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 1, Issue , 2005, Pages 7-12

  Witarsa, David ^a   Soundarapandian, Mohanraj ^a   Yoon, Seung Wook ^a   Kripesh, Vaidyanathan ^a   Weng, Teoh Kum ^a   Nagarajan, Ranganathan ^a   Khan, Oratti Kalandar Navas ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

CHIP STACKING TECHNOLOGY; MULTIFUNCTIONAL CHIPS; SILICON BASED SYSTEM IN PACKAGE (SIP); TURN-AROUND TIME;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 33845582687     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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