Modeling board-level four-point bend fatigue and impact drop tests

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 443-448

  Che, F X ^a   Pang, John H L ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COPPER; CYCLIC LOADS; MATHEMATICAL MODELS; SILVER; SOLDERED JOINTS; THERMAL EFFECTS; TIN;

CYCLIC BENDING; DROP TESTS; FATIGUE RESISTANCE;

FATIGUE OF MATERIALS;

EID: 33845567770     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645684     Document Type: Conference Paper

References (10)

1. Shetty, S. et al., "Fatigue of Chip Scale Package Interconnects Due to Cyclic Bending", Journal of Electronic Packaging, Vol. 123, (2001), pp. 302-308.
2. Shetty, S. and Reinikainen, T., "Three- and Four-Point Bend Testing for Electronic Packages", Journal of Electronic Packaging, Vol. 125, (2003), pp. 556-561.
3. th Electronic Components and Technology Conf, Las Vegas, June. 2004, pp. 1279-1287.
4. nd Electronic Components and Technology Conf, 2002, pp. 974-978.
5. JEDEC Standard, JESD22-B111: Board Level Drop Test Method of Components for Handheld Electronic Products, 2003.
6. JEDEC Standard, IPC/JEDEC-9702: Monotonic Bend Characterization of Board-Level Interconnects, 2004.
7. th Electronics Packaging Technology Conf, Singapore, December. 2004, pp. 787-792.
8. st Electronic Components and Technology Conf, 2001, pp. 606-612.
9. th Electronic Components and Technology Con, 2005, pp.916-921.
10. th Electronic Components and Technology Conf, 2006.