Three- and four-point bend testing for electronic packages

Journal of Electronic Packaging

Volumn 125, Issue 4, 2003, Pages 556-561

  Shetty, Santosh ^a   Reinikainen, Tommi ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; FINITE ELEMENT METHOD; MATERIALS TESTING; MICROPROCESSOR CHIPS; PRINTED CIRCUIT BOARDS;

FOUR POINT BEND TESTING; PACKAGE CONSTRUCTIONAL DETAILS; THREE POINT BEND TESTING;

CHIP SCALE PACKAGES;

EID: 0347567450     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.1604158     Document Type: Article

References (6)

1. Darveaux, R., and Banerji, K., 1992, "Constitutive Relations for Tin Based Solder Joints," Electronic Components and Technology Conference, San Diego, California, May 18-20, pp. 538-551.
2. Darveaux, R. 2000, "Effect of Simulation Methodology on Solder Joint Crack Growth Correlation," Electronic Components and Technology Conference, Las Vegas, Nevada, May 21-24, pp. 1048-1058.
3. Darveaux, R., 1997, "Solder Joint Fatigue Life Model," Proceedings TMS.
4. Shetty, S., Dasgupta, A., Halkola, V., Lehtinen, V., Reinikainen, T., 2000, "Bending Fatigue Of Chip Scale Package Interconnects," ASME International Mechanical Engineering Congress and Exposition, Orlando, Florida, Nov. 5-10.
5. Shetty, S., 2000, "Effect Of Cyclic Bending On Chip Scale Package Assemblies," M.S. thesis, Dept. of Mechanical Engineering, University of Maryland, College Park.
6. Zhu, J., 1999, "Three-Dimensional Effects of Solder Joints in Micro-Scale BGA Assembly," ASME J. Electron. Packag., 121, pp. 121-302.