Estimating the utilization of embedded FPGA co-processor

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 214-221

  Qu, Yang ^a   Soininen, J P ^a  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COPROCESSOR; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL SYNTHESIS; MOTION PICTURE EXPERTS GROUP STANDARDS; RECONFIGURABLE HARDWARE; SYSTEMS ANALYSIS;

ESTIMATION APPROACHES; ESTIMATION ERRORS; ESTIMATION TECHNIQUES; FORCE-DIRECTED SCHEDULING; HARDWARE IMPLEMENTATIONS; RESOURCE UTILIZATIONS; SOFTWARE IMPLEMENTATION; SYSTEM DESIGNERS;

SYSTEM-ON-CHIP;

ALGORITHMS; COMPUTER PROGRAMS; ELECTRIC CIRCUITS; SCHEDULING;

EID: 33845293026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231929     Document Type: Conference Paper

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