Predicting System-Level Area and Delay for Pipelined and Nonpipelined Designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 8, 1992, Pages 955-965

  Jain, Rajiv ^a   Parker, Alice C ^b   Park, Nohbyung ^c  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^c Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; DATA PROCESSING--DATA TRANSFER; MATHEMATICAL MODELS;

DATA FLOW GRAPHS; DATA PATH SYNTHESIS;

COMPUTER SYSTEMS, DIGITAL;

EID: 0026903189     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.149767     Document Type: Article

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