메뉴 건너뛰기




Volumn 3, Issue , 2006, Pages 86-89

Three-dimensional simulation of polysilicon thin film transistors with single-, double- and surrounding-gate structures

Author keywords

Double gate; Modeling and simulation; Polysilicon TFTs; Single gate; Surrounding gate

Indexed keywords

COMPUTER SIMULATION; CONTROLLABILITY; ELECTRONIC STRUCTURE; LEAKAGE CURRENTS; MATHEMATICAL MODELS; POLYSILICON;

EID: 33845200643     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (20)
  • 1
    • 0003690029 scopus 로고    scopus 로고
    • High performance low-temperature processes polysilicon TFTs fabricated by excimer laser crystallization with recessed-channel structure
    • H.-C. Cheng, L.-J. Cheng, C.-W. Lin, Y.-L Lu, and C.-Y. Chen, "High performance low-temperature processes polysilicon TFTs fabricated by excimer laser crystallization with recessed-channel structure," IEEE AMLCD Tech. Dig, 281, 2000.
    • (2000) IEEE AMLCD Tech. Dig , pp. 281
    • Cheng, H.-C.1    Cheng, L.-J.2    Lin, C.-W.3    Lu, Y.-L.4    Chen, C.-Y.5
  • 4
    • 0001128089 scopus 로고
    • Characterization of trapping states in polycrystalline-silicon thin film transistors by deep level transient spectroscopy
    • J. R. Ayres, "Characterization of trapping states in polycrystalline-silicon thin film transistors by deep level transient spectroscopy," Journal of Applied Physics, 74, 1787, 1993.
    • (1993) Journal of Applied Physics , vol.74 , pp. 1787
    • Ayres, J.R.1
  • 6
    • 0025519501 scopus 로고
    • Analytical models of subthreshold swing and threshold voltage for thin and ultra-thin film SOI MOSFET's
    • F. Balestra, M. Benachir, J. Brini, and G. Chibaudo, "Analytical models of subthreshold swing and threshold voltage for thin and ultra-thin film SOI MOSFET's," IEEE Trans. Electron Devices, 37, 2303, 1990.
    • (1990) IEEE Trans. Electron Devices , vol.37 , pp. 2303
    • Balestra, F.1    Benachir, M.2    Brini, J.3    Chibaudo, G.4
  • 7
    • 23644461733 scopus 로고
    • Physical basis of scattering potential at grain boundary of polycrystalline semiconductors
    • C. W. Wu and E. S. Yang, "Physical basis of scattering potential at grain boundary of polycrystalline semiconductors," Appl. Phys. Lett., 40, 49, 1982.
    • (1982) Appl. Phys. Lett. , vol.40 , pp. 49
    • Wu, C.W.1    Yang, E.S.2
  • 8
    • 0002439038 scopus 로고
    • Electrical and electronical properties of grain boundaries in silicon
    • H. J. Queisser and J. Werner, "Electrical and electronical properties of grain boundaries in silicon," Mat. Res. Soc. Symp. Proc., 106, 53, 1988.
    • (1988) Mat. Res. Soc. Symp. Proc. , vol.106 , pp. 53
    • Queisser, H.J.1    Werner, J.2
  • 10
    • 0023541755 scopus 로고
    • Inversion-mode MOSFET's in polycrystalline silicon thin films: Characterization and modeling
    • F. Qian, D. M. Kim, H. K. Park, and J. L. Sachitano, "Inversion-mode MOSFET's in polycrystalline silicon thin films: Characterization and modeling," IEEE Trans. Electron Devices, ED-35, 2439, 1987.
    • (1987) IEEE Trans. Electron Devices , vol.ED-35 , pp. 2439
    • Qian, F.1    Kim, D.M.2    Park, H.K.3    Sachitano, J.L.4
  • 11
    • 0020796133 scopus 로고
    • Effects of grain boundaries on the channel conductance of SOI MOSFET's
    • J. G. Fossum and A. Ortiz-Conde, "Effects of grain boundaries on the channel conductance of SOI MOSFET's," IEEE Trans. Electron Devices, ED-30,933, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 933
    • Fossum, J.G.1    Ortiz-Conde, A.2
  • 12
    • 0025955121 scopus 로고
    • Polysilicon thin film transistors with channel length and width comparable to or smaller than the grain size of the thin film
    • N. Yamauchi, J.-J. J. Hajjar, and R. Reif, "Polysilicon thin film transistors with channel length and width comparable to or smaller than the grain size of the thin film," IEEE Trans. Electron Devices, 38, 55, 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 55
    • Yamauchi, N.1    Hajjar, J.-J.J.2    Reif, R.3
  • 13
    • 0038009941 scopus 로고    scopus 로고
    • Investigation of Gate-Induced Drain Leakage (GIDL) current in thin body devices: Single-gate ultra-thin body, symmetrical double-gate, and asymmetrical double-gate MOSFETs
    • Y.-K. Choi, D. Ha, T.-J. King and J. Bokor, "Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs," Japanese Journal of Applied Physics, 42, 2073, 2003.
    • (2003) Japanese Journal of Applied Physics , vol.42 , pp. 2073
    • Choi, Y.-K.1    Ha, D.2    King, T.-J.3    Bokor, J.4
  • 17
    • 0242332710 scopus 로고    scopus 로고
    • Sensitivity of double-gate and FinFET devices to process variations
    • S. Xiong and J. Bokor, "Sensitivity of Double-Gate and FinFET Devices to Process Variations," IEEE Transactions on Electron Devices, 50, 2255, 2003.
    • (2003) IEEE Transactions on Electron Devices , vol.50 , pp. 2255
    • Xiong, S.1    Bokor, J.2
  • 18
    • 3142751898 scopus 로고    scopus 로고
    • A two-dimensional quantum transport simulation of nanoscale double-gate MOSFETs using parallel adaptive technique
    • Y. Li and S.-M. Yu, "A Two-Dimensional Quantum Transport Simulation of Nanoscale Double-Gate MOSFETs using Parallel Adaptive Technique," IEICE Transactions on Information and Systems, E87-D, 1751, 2004.
    • (2004) IEICE Transactions on Information and Systems , vol.E87-D , pp. 1751
    • Li, Y.1    Yu, S.-M.2
  • 19
    • 0037810872 scopus 로고    scopus 로고
    • A parallel monotone iterative method for the numerical solution of multidimensional semiconductor poisson equation
    • Y. Li, "A Parallel Monotone Iterative Method for the Numerical Solution of Multidimensional Semiconductor Poisson Equation," Computer Physics Communications, 153, 359, 2003.
    • (2003) Computer Physics Communications , vol.153 , pp. 359
    • Li, Y.1
  • 20
    • 0036361047 scopus 로고    scopus 로고
    • A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation
    • Y. Li, S. M. Sze, and T.-S. Chao, "A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation," Engineering with Computers, 18, 124, 2002.
    • (2002) Engineering with Computers , vol.18 , pp. 124
    • Li, Y.1    Sze, S.M.2    Chao, T.-S.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.