Random modulation: Multi-threshold-voltage design methodology in sub-2-V power supply CMOS

IEICE Transactions on Electronics

Volumn E83-C, Issue 11, 2000, Pages 1747-1753

  Kato, Naoki ^a   Akita, Yohei ^a   Hiraki, Mitsuru ^a   Yamashita, Takeo ^a   Shimizu, Teruhisa ^a   Maki, Fuyuhiko ^a   Yano, Kazuo ^a  

^a HITACHI LTD   (Japan)

Author keywords

CMOS; Leakage current; Low power; Threshold voltage

Indexed keywords

EID: 0000628423     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

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