A routing algorithm for flip-chip design

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 753-758

  Fang, Jia Wei ^a   Lin, I Jye ^a   Yuh, Ping Hung ^a   Chang, Yao Wen ^a   Wang, Jyh Herng ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b FARADAY TECHNOLOGY CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; PROBLEM SOLVING; ROUTERS; SYSTEMS ANALYSIS;

NETWORK FLOW ALGORITHMS; ROUTING ALGORITHMS;

CHIP SCALE PACKAGES;

EID: 33751400036     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560165     Document Type: Conference Paper

References (17)

1. D. Chang, T. F. Gonzalez, and O. H. Ibarra, "A Flow Based Approach to the Pin Redistribution Problem for Multi-Chip Modules," Proc. GVLSI, pp. 114-119, 1994.
2. B. Cherkasssky, "Efficient Algorithms for the Maximum Flow Problem," Mathematical Methods for the Solution of Economical Problems, vol. 7, pp. 117-126, 1977.
3. S.-S. Chen, J.-J. Chen, S.-J. Chen, and C.-C. Tsai, "An Automatic Router for the Pin Grid Array Package," Proc. ASP-DAC, pp. 133-136, 1999.
4. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms, MIT Press, 2000.
5. M.-F. Yu and W.-M. Dai, "Pin Assignment and Routing on a Single-Layer Pin Grid Array," Proc. ASPDAC, pp. 203-208, 1995.
6. C.-P. Hsu, "General River Routing Algorithm," Proc. DAC, pp. 578-583, 1983.
7. J. Hu and S. S. Sapatnekar, "A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets," Proc. ICCAD, pp. 99-103, 2000.
8. Y. Kubo and A. Takahashi, "A Global Routing Method for 2-Layer Ball Grid Array Packages," Proc. ISPD, pp. 36-43, 2005.
9. E. S. Kuh, T. K. Kashiwabara, and T. Fujisawa, "On Optimum Single Row Routing," IEEE Transactions on Circuits and Systems, vol. 26, pp. 361-368, 1979.
10. A. Titus, B. Jaiswal, T. J. Dishongh, and A. N. Cartwright, "Innovative Circuit Board Level Routing Designs for BGA Packages," IEEE Transactions on Advanced Packaging, vol. 27, pp. 630-639, 2004.
11. C.-C. Tsai, C.-M. Wang, and S.-J. Chen, "NEWS: A Net-Even-Wiring System for the Routing on a Multilayer PGA Package," IEEE Transactions on Computer-Aided Design, vol. 17, pp. 182-189, 1998.
12. S.-S. Chen, J.-J. Chen, C.-C. Tsai, and S.-J. Chen, "An Even Wiring Approach to the Ball Grid Array Package Routing," Proc. ICCD, pp. 303-306, 1999.
13. UMC, "0.13μm Flip Chip Layout Guideline," pp. 6, 2004.
14. D. Wang, P. Zhang, C.-K. Chang, and A. Sen, "A Performance-Driven I/O Pin Routing Algorithm," Proc. ASP-DAC, pp. 129-132, 1999.
15. X. Xiang, X. Tang, and D.-F. Wang, "Minimum-Cost Flow-Based Algorithm for Simultaneous Pin Assignment and Routing," IEEE Transactions on Computer-Aided Design, vol. 22, pp. 870-878, 2003.
16. M.-F. Yu and W.-M. Dai, "Single-Layer Fanout Routing and Routability Analysis for Ball Grid Arrays," Proc. ICCAD, pp. 581-586, 1995.
17. M.-F. Yu, J. Darnauer and W.-M. Dai, "Interchangeable Pin Rouing with Application to Package Layout," Proc. ICCAD, pp. 668-673, 1996.