A performance-driven I/O pin routing algorithm

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1999-January, Issue , 1999, Pages 129-132

  Wang, Dongsheng ^a   Zhang, Ping ^a   Cheng, Chung Kuan ^a   Sen, Arunabha ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COST FUNCTIONS; ROUTING ALGORITHMS;

FLOW DISTRIBUTION; MAX FLOW ALGORITHM; PERFORMANCE-DRIVEN; PHYSICAL ROUTING; ROUTING PROCESS; SMOOTH CURVES; TOPOLOGICAL ROUTING; WEIGHT FUNCTIONS;

WIRE;

EID: 85027145929     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.1999.759779     Document Type: Conference Paper

References (6)

1. "The National Technology Roadmap for Semiconductors", by Semiconductor Industry Association, 1994.
2. Chia-Chun Tsai, Sao-Jie Chen, "Planar Routing on A Pin Grid Array Package". ICCAD/Graphics'93, Beijing, pp.439-444, 1993.
3. P571-575, 1993.
4. M.F. Yu, W.W. Dai, "Single-Layer Fanout Routing and Routability Analysis for Ball Grid Arrays", ICCAD'95, pp.581-586, 1995.
5. M.F. Yu, J. Darnauer, W.W. Dai, "Interchangeable Pin Routing with Application to Package Layout", ICCAD'96, pp.668-673, 1996.
6. Kennington, Helgason, "Algorithms for Network Programming", John Wiley & Sons, 1980.