Min-cost flow-based algorithm for simultaneous pin assignment and routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 7, 2003, Pages 870-878

  Xiang, Hua ^a   Tang, Xiaoping ^b   Wong, Martin D F ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Detail routing; Global routing; Min cost flow; Physical design; Pin assignment; Routing

Indexed keywords

ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTATIONAL COMPLEXITY; ITERATIVE METHODS; POLYNOMIALS; THEOREM PROVING; VLSI CIRCUITS;

ENGINEERING CHANGE ORDER; PIN ASSIGNMENT; POLYNOMIAL-TIME EXACT ALGORITHM; ROUTING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038444648     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.814258     Document Type: Article

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