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Volumn 2006, Issue , 2006, Pages 2-7

The impacts of untestable defects on transition fault testing

Author keywords

[No Author keywords available]

Indexed keywords

ATPG PROCEDURES; STUCK-OPEN FAULTS; TRANSITION FAULT TEST SET;

EID: 33751074464     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.87     Document Type: Conference Paper
Times cited : (6)

References (18)
  • 2
    • 0024108354 scopus 로고
    • A CMOS fault extractor for inductive fault analysis
    • Nov.
    • F.J. Ferguson and J.P. Shen, "A CMOS Fault Extractor for Inductive Fault Analysis," in IEEE Trans. on CAD, Vol. 7, NO. 11, pp. 1181-1194, Nov. 1988.
    • (1988) IEEE Trans. on CAD , vol.7 , Issue.11 , pp. 1181-1194
    • Ferguson, F.J.1    Shen, J.P.2
  • 3
    • 0031186626 scopus 로고    scopus 로고
    • The future of test and DFT
    • Jul.-Sep.
    • G. Singer, "The Future of Test and DFT," in IEEE Design and Test, pp.11-14, Jul.-Sep. 1997.
    • (1997) IEEE Design and Test , pp. 11-14
    • Singer, G.1
  • 4
    • 0017961684 scopus 로고
    • Fault modeling and logic simulation of CMOS and MOS integrated circuits
    • R.L. Wadsack, "Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits," in Bell. System Tech. J., Vol. 57, No. 5, pp. 1449-1474, 1978.
    • (1978) Bell. System Tech. J. , vol.57 , Issue.5 , pp. 1449-1474
    • Wadsack, R.L.1
  • 5
    • 0022766854 scopus 로고
    • Testable realizations for FET stuck-open faults in CMOS combinational logic circuits
    • Aug.
    • S.M. Reddy and M.K. Reddy, "Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits," in IEEE Trans. on Computer., Vol. C-35, No. 8, pp. 742-754, Aug. 1986.
    • (1986) IEEE Trans. on Computer. , vol.C-35 , Issue.8 , pp. 742-754
    • Reddy, S.M.1    Reddy, M.K.2
  • 6
    • 33751072538 scopus 로고
    • Automatic test generation for stuck-open faults in CMOS VLSI
    • Y.M. Elziq, "Automatic Test Generation for Stuck-Open Faults in CMOS VLSI,", in Intl. Test Conf., pp. 347-354, 1981.
    • (1981) Intl. Test Conf. , pp. 347-354
    • Elziq, Y.M.1
  • 8
    • 33744638649 scopus 로고
    • Some relationships between delay testing and stuck-open testing in CMOS circuits
    • R. David, S. Rahal, J.-L. Rainard, "Some Relationships Between Delay Testing and Stuck-Open Testing in CMOS Circuits," in European Design Auto. Conf., pp. 339-343, 1990.
    • (1990) European Design Auto. Conf. , pp. 339-343
    • David, R.1    Rahal, S.2    Rainard, J.-L.3
  • 9
    • 0024122316 scopus 로고
    • Stuck-open and transition fault testing in CMOS complex gates
    • H. Cox and J. Rajski, "Stuck-Open and Transition Fault Testing in CMOS Complex Gates," in Intl. Test Conf., pp. 688-694, 1988.
    • (1988) Intl. Test Conf. , pp. 688-694
    • Cox, H.1    Rajski, J.2
  • 10
    • 0022089113 scopus 로고
    • A practical approach to fault simulation and test generation for bridging faults
    • Jul.
    • M. Abramovici and M. Breuer, "A Practical Approach to Fault Simulation and Test Generation for Bridging Faults," in IEEE Tran. on Comp., C-34, 658-663, Jul. 1985.
    • (1985) IEEE Tran. on Comp. , vol.C-34 , pp. 658-663
    • Abramovici, M.1    Breuer, M.2
  • 11
    • 0024122852 scopus 로고
    • Detecting bridging faults with stuck-at test sets
    • S.D. Millman and E.J. McCluskey, "Detecting Bridging Faults with Stuck-At Test Sets," in Intl. Test Conf., pp. 773-783, 1988.
    • (1988) Intl. Test Conf. , pp. 773-783
    • Millman, S.D.1    McCluskey, E.J.2
  • 12
    • 0027833778 scopus 로고
    • Fast and accurate CMOS bridging fault simulation
    • J. Rearick and J.H. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," in Intl. Test Conf., pp.54-62, 1993.
    • (1993) Intl. Test Conf. , pp. 54-62
    • Rearick, J.1    Patel, J.H.2
  • 13
    • 0027883887 scopus 로고
    • Biased voting: A method for simulation CMOS bridging faults in the presence of variable gate logic thresholds
    • P.C. Maxwell and R.C. Aitken, "Biased Voting: A Method for simulation CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," in Intl. Test Conf., pp. 63-72, 1993.
    • (1993) Intl. Test Conf. , pp. 63-72
    • Maxwell, P.C.1    Aitken, R.C.2
  • 14
    • 0033318725 scopus 로고    scopus 로고
    • Accurate fault modeling and fault simulation of resistive bridges
    • V.R. Sar-Dessai, D.M.H. Walker, "Accurate Fault Modeling and Fault Simulation of Resistive Bridges," in Intl. Test Conf., pp. 596-605, 1999.
    • (1999) Intl. Test Conf. , pp. 596-605
    • Sar-Dessai, V.R.1    Walker, D.M.H.2
  • 15
    • 0033300347 scopus 로고    scopus 로고
    • On detecting bridges causing timing failures
    • S. Mandava, S. Chakravarty, and S. Kundu, "On Detecting Bridges Causing Timing Failures," in Proc. ICCD, pp. 400-406, 1999.
    • (1999) Proc. ICCD , pp. 400-406
    • Mandava, S.1    Chakravarty, S.2    Kundu, S.3
  • 16
    • 0033354540 scopus 로고    scopus 로고
    • A comparison of bridging fault simulation methods
    • S. Ma, I. Shaik, R.S. Fetherston, "A Comparison of Bridging Fault Simulation Methods," in Intl. Test Conf., pp. 587-595, 1999.
    • (1999) Intl. Test Conf. , pp. 587-595
    • Ma, S.1    Shaik, I.2    Fetherston, R.S.3
  • 17
    • 84948428485 scopus 로고    scopus 로고
    • Fault models for speed failures caused by bridges and opens
    • S. Chakravarty and A. Jain, "Fault Models for Speed Failures Caused by Bridges and Opens," in VLSI Test Symp., pp.373-378, 2002.
    • (2002) VLSI Test Symp. , pp. 373-378
    • Chakravarty, S.1    Jain, A.2
  • 18
    • 0036443088 scopus 로고    scopus 로고
    • Experimental evaluation of scan tests for bridges
    • S. Chakravarty, el. al., "Experimental Evaluation of Scan Tests for Bridges," in Intl. Test Conf., pp.509-518, 2002.
    • (2002) Intl. Test Conf. , pp. 509-518
    • Chakravarty, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.