Yield enhancement of asynchronous logic circuits through 3-Dimensional integration technology

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn 2006, Issue , 2006, Pages 159-164

  Peng, Song ^a   Manohar, Rajit ^a  

^a Cornell University ^*  (United States)

Author keywords

3D integration; Asynchronous circuits; Defect tolerance; Self reconfiguration; Yield

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT LAYOUT; THREE DIMENSIONAL;

3D INTEGRATION; ASYNCHRONOUS CIRCUITS; DEFECT TOLERANCE; SELF RECONFIGURATION; YIELD ENHANCEMENT;

LOGIC CIRCUITS;

EID: 33750912427     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127947     Document Type: Conference Paper

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