The routability of multiprocessor network topologies in FPGAs

International Workshop on System Level Interconnect Prediction, SLIP

Volumn 2006, Issue , 2006, Pages 49-56

  Saldaña, Manuel ^a   Shannon, Lesley ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

FPGA; Interconnect; Multiprocessor; Network on chip; Topology

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL CIRCUITS; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PARAMETER ESTIMATION; ROUTERS; TOPOLOGY;

INTERCONNECTS; NETWORK ON CHIPS; RESOURCE UTILIZATION; ROUTING RESOURCES;

INTERCONNECTION NETWORKS;

EID: 33750904591     PISSN: None     EISSN: 15445631     Source Type: Conference Proceeding    
DOI: 10.1145/1117278.1117290     Document Type: Conference Paper

References (17)

1. ARM Corporation. "AMBA specification". [online] 1999. www.arm.com (Accessed: 2005).
2. IBM Corporation. "The Coreconnect Bus Architecture", [online] 1999. www.chips.ibm.com (Accessed: 2005).
3. OpenCoros.org. "The WISHBONE System Architecture". [online] 2002. opencoros.org/projects.cgi/web/wishbone (Accessed: 2005).
4. Sonics Inc. (online). www.sonicsinc.com/sonics/products/ siliconbackplaneIII/(Accessed: 2005).
5. G. de Micheli and L. Benini. Networks on chip: A new paradigm for systems on chip design. In DATE '02: Proceedings of the conference on Design, automation and test in Europa, page 418, Washington, DC, USA, 2002. IEEE Computer Society.
6. S Kumar, A Jantsch, J Soininen, M Forsell, M Millberg, J Oberg, K Tiensyrja, and A Hemani. A network on chip architecture and design methodology. In VLSI, 2002. Proceedings. IEEE Computer Society Annual Symposium on, pages 105-112, Pittsburgh, USA, 2002. IEEE Computer Society.
7. Adrijean Adriahantenaina, Herve Charlery, Alain Greiner, Laurent Mortiez, and Cesar Albenes Zeferino. Spin: A scalable, packet switched, on-chip micro-network, In DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, page 20070, Washington, DC, USA, 2003. IEEE Computer Society.
8. Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, and Resve Saleh. Performance evaluation and design trade-offs for network-on-chip interconnect architectures. IEEE Trans. Comput., 54(8):1025-1040, 2005.
9. William J. Dally and Brian Towles. Route packets, not wires: on-chip interconnection networks. In DAC '01: Proceedings of the 38th conference on Design, automation, pages 684-689, New York, NY, USA, 2001. ACM Press.
10. G. Brebner and D. Levi, Networking on Chip with Platform FPGAs. In Field-Programmable Technology (FPT), Proceedings. 2003 IEEE International Conference on, pages 13-20, July 2003.
11. Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Lenpers, Gerd Ascheid, Heinrich Meyr, and Serge Goosseus. A modular simulation framework for architectural exploration of on-chip interconnection networks. In CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pages 7-12, New York, NY, USA, 2003. ACM Press.
12. Davide Bertozzi and Antoine Jalabert. NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systenis-on-Chip. IEEE Trans. Parallel Distrib. Syst., 16(2):113-129, 2005.
13. Charles L. Seitz. Let's route packets instead of wires. In AUSCRYPT '90: Proceedings of the sixth MIT conference on Advanced research in VLSI, pages 133-138, Cambridge, MA, USA, 1990. MIT Press.
14. T.A. Bartic, J.Y. Mignolet, T. Marescaux, D. Verkest, S Vernalde, and R. Lauwereins. Topology adaptive network-on-chip design and implementation. In Computer and Digital Tecniques, IEEE Proceedings, pages 467-472. IEE Proceedings, July 2005.
15. J Duato and L Yalamanchili Ni. Interconnection Networks, an Engineering Approach. Computer Society Press, Los Alamitos, California, 1998.
16. Xilinx, Inc. http://www.xilinx.com.
17. ModelSim Home Page, [online] September 2005. http://www.model.com/.