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1
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84961683038
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A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM
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San Francisco
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Higashi K, Nakamura N, Miyajima H, Satoh S, Kojima A, Abe J, Nagahata Y, Tatsumi T, Tabuchi K, Hasegawa T, Kawashima H, Arakawa S, Matsunaga N, Shibata H. A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM. Proc 2002 Int Interconnect Tech Conf, p 15-17, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 15-17
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Higashi, K.1
Nakamura, N.2
Miyajima, H.3
Satoh, S.4
Kojima, A.5
Abe, J.6
Nagahata, Y.7
Tatsumi, T.8
Tabuchi, K.9
Hasegawa, T.10
Kawashima, H.11
Arakawa, S.12
Matsunaga, N.13
Shibata, H.14
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2
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84961692329
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Integration of Cu/SiOC in dual damascene interconnect for 0.1 μm technology using a new SiC material as dielectric barrier
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San Francisco
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Fayolle M, Torres J, Passemard G, Fusalba F, Fanget G, Louis D, Arnaud L, Girault V, Cluzel J, Feldis H, Rivoire M, Louveau O, Mourier T, Broussous L. Integration of Cu/SiOC in dual damascene interconnect for 0.1 μm technology using a new SiC material as dielectric barrier. Proc 2002 Int Interconnect Tech Conf, p 39-41, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 39-41
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Fayolle, M.1
Torres, J.2
Passemard, G.3
Fusalba, F.4
Fanget, G.5
Louis, D.6
Arnaud, L.7
Girault, V.8
Cluzel, J.9
Feldis, H.10
Rivoire, M.11
Louveau, O.12
Mourier, T.13
Broussous, L.14
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3
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84961743038
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Dual damascene patterning for full spin-on stack of porous low-k material
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San Francisco
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Furukawa Y, Kokubo T, Struyf H, Maenhoudt M, Vanhaelemeersch S, Gravesteijn D. Dual damascene patterning for full spin-on stack of porous low-k material. Proc 2002 Int Interconnect Tech Conf, p 45-47, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 45-47
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Furukawa, Y.1
Kokubo, T.2
Struyf, H.3
Maenhoudt, M.4
Vanhaelemeersch, S.5
Gravesteijn, D.6
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4
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84961744658
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Adhesion studies of thin films on ultra low-k
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San Francisco
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Maitrejean S, Fusalba F, Patz M, Jousseaume V, Mourier T. Adhesion studies of thin films on ultra low-k. Proc 2002 Int Interconnect Tech Conf, p 206-208, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 206-208
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Maitrejean, S.1
Fusalba, F.2
Patz, M.3
Jousseaume, V.4
Mourier, T.5
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5
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33750884446
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Electron-beam cure process for porous low-k materials
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Tokyo
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Mitsuoka K, Iwasaki M, Honda M, Ohnishi T, Fujita K, Miyajima H, Nakata R, Hayasaka N. Electron-beam cure process for porous low-k materials. Extended Abstracts of Advance Metallization Conference 2003: Asian Session, p 16-17, Tokyo.
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Extended Abstracts of Advance Metallization Conference 2003: Asian Session
, pp. 16-17
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Mitsuoka, K.1
Iwasaki, M.2
Honda, M.3
Ohnishi, T.4
Fujita, K.5
Miyajima, H.6
Nakata, R.7
Hayasaka, N.8
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6
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33750874755
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Effect of diffusion barriers on electrical performance and reliability of Cu metallization in 0.13 μm Cu/ultra-low-k (porous-SiLK, k = 2.2) technology
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Tokyo
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Li CY, Zhang DH, Lu PW, Su SS, He X, Balakumar S, Seah CH, Chen YW, Chen XT, Babu N, Murthy BR, Roy MM, Kumar R. Effect of diffusion barriers on electrical performance and reliability of Cu metallization in 0.13 μm Cu/ultra-low-k (porous-SiLK, k = 2.2) technology. Extended Abstracts of Advance Metallization Conference 2003: Asian Session, p 20-21, Tokyo.
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Extended Abstracts of Advance Metallization Conference 2003: Asian Session
, pp. 20-21
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Li, C.Y.1
Zhang, D.H.2
Lu, P.W.3
Su, S.S.4
He, X.5
Balakumar, S.6
Seah, C.H.7
Chen, Y.W.8
Chen, X.T.9
Babu, N.10
Murthy, B.R.11
Roy, M.M.12
Kumar, R.13
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7
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33750873342
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New materials and processing techniques for next-generation LSI multi-increase circuits, No. 2 printing
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Yoshikawa K (editor in chief). Technical Information Publishers p 14-15
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Yoshikawa K (editor in chief). New materials and processing techniques for next-generation LSI multi-increase circuits, No. 2 printing. Technical Information Publishers; 2001. p 14-15, 173-197.
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(2001)
, pp. 173-197
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8
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84961683817
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Development of 300 mm low-k dielectric for 0.13 μm BEOL damascene process
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San Francisco
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Lu LC, Chang W, Jang SM, Yu CH, Liang MS. Development of 300 mm low-k dielectric for 0.13 μm BEOL damascene process. Proc 2002 Int Interconnect Tech Conf, p 63-65, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 63-65
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Lu, L.C.1
Chang, W.2
Jang, S.M.3
Yu, C.H.4
Liang, M.S.5
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9
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33750857971
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Development of defect free post - CMP cleaning in Cu damascene wiring
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Tokyo
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Nishioka Y, Ariga Y, Inoue T, Tokushige K, Tsujimura M. Development of defect free post - CMP cleaning in Cu damascene wiring. Extended Abstracts of Advance Metallization Conference 2003: Asian Session, p 84-85, Tokyo.
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Extended Abstracts of Advance Metallization Conference 2003: Asian Session
, pp. 84-85
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Nishioka, Y.1
Ariga, Y.2
Inoue, T.3
Tokushige, K.4
Tsujimura, M.5
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10
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84888229557
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Post-CMP cleaning challenge for Cu CMP at the sub-90 nm node
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Micro Contamination Center, Northeastern University, Boston
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Small B, Shang C, Scott B. Post-CMP cleaning challenge for Cu CMP at the sub-90 nm node. 2nd Int Surface Cleaning Workshop, Micro Contamination Center, Northeastern University, Boston, 2003.
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(2003)
2nd Int Surface Cleaning Workshop
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Small, B.1
Shang, C.2
Scott, B.3
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11
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33750888128
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Removing contaminants from wafer edge, back side and hydrophobic front side in post-CMP cleaning system
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Marina del Rey, USA
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Ravkin M, Larios J, Farber J. Removing contaminants from wafer edge, back side and hydrophobic front side in post-CMP cleaning system. Proc VLSI/ULSI Multilevel Interconnection Conference, p 262-266, Marina del Rey, USA, 2003.
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(2003)
Proc VLSI/ULSI Multilevel Interconnection Conference
, pp. 262-266
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Ravkin, M.1
Larios, J.2
Farber, J.3
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12
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33750853867
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Fundamentals and improvements of OSG low-k dielectric/oxide interface adhesion and post-scrubber defect removal performance evaluation
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Marina del Rey, USA
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Chen LL, Lin CH, Li LP, Lu YC, Jang SM, Liang MS. Fundamentals and improvements of OSG low-k dielectric/oxide interface adhesion and post-scrubber defect removal performance evaluation. Proc VLSI/ULSI Multilevel Interconnection Conference, p 36-42, Marina del Rey, USA, 2003.
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(2003)
Proc VLSI/ULSI Multilevel Interconnection Conference
, pp. 36-42
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Chen, L.L.1
Lin, C.H.2
Li, L.P.3
Lu, Y.C.4
Jang, S.M.5
Liang, M.S.6
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13
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33750872559
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Improved post-CMP cleaning technique for defect free damascene structure
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Micro Contamination Center, Northeastern University, Boston
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Kodera M, Uekusa S, Miyashita N, Nishioka Y, Inoue T, Tokushige K, Tsujimura M. Improved post-CMP cleaning technique for defect free damascene structure. 2nd Int Surface Cleaning Workshop, Micro Contamination Center, Northeastern University, Boston, 2003.
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(2003)
2nd Int Surface Cleaning Workshop
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Kodera, M.1
Uekusa, S.2
Miyashita, N.3
Nishioka, Y.4
Inoue, T.5
Tokushige, K.6
Tsujimura, M.7
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14
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4043120567
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The development of defect free post - CMP cleaning in Cu/low-k damascene wiring
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Conf Proc AMC XIX © 2004 Mater Res Soc
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Nishioka Y, Inoue T, Tokushige K, Tsujimura M. The development of defect free post - CMP cleaning in Cu/low-k damascene wiring. Advance Metallization Conference 2003 (AMC 2003), Conf Proc AMC XIX © 2004 Mater Res Soc, p 645-649, 2003.
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(2003)
Advance Metallization Conference 2003 (AMC 2003)
, pp. 645-649
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Nishioka, Y.1
Inoue, T.2
Tokushige, K.3
Tsujimura, M.4
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15
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4944240085
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Surface analysis of Cu after chemical-mechanical planarization
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Kodera M, Uekusaka S-I, Minakawa S, Nishioka Y, Fukunaga A, Tsujimura M. Surface analysis of Cu after chemical-mechanical planarization. Electrochem Eng Phys Chem Electrochem Soc 2004;72:569-576.
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(2004)
Electrochem Eng Phys Chem Electrochem Soc
, vol.72
, pp. 569-576
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Kodera, M.1
Uekusaka, S.-I.2
Minakawa, S.3
Nishioka, Y.4
Fukunaga, A.5
Tsujimura, M.6
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17
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84961744604
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Cu/LKD-5109 damascene integration demonstration using FF-02 low-k spin-on hard-mask and embedded etch-stop
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San Francisco
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Kokubo T, Das A, Furukawa Y, Vos I, Iacopi F, Stryyf H, Aelst JV, Maenhoudt M, Tokei Z, Vervoort I, Bender H, Stucchi M, Schaekers M, Boullart W, Van Hove M, Vanhaelemeersch S, Peterson W, Shiota A, Maex K. Cu/LKD-5109 damascene integration demonstration using FF-02 low-k spin-on hard-mask and embedded etch-stop. Proc 2002 Int Interconnect Tech Conf, p 51-53, San Francisco.
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Proc 2002 Int Interconnect Tech Conf
, pp. 51-53
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Kokubo, T.1
Das, A.2
Furukawa, Y.3
Vos, I.4
Iacopi, F.5
Stryyf, H.6
Aelst, J.V.7
Maenhoudt, M.8
Tokei, Z.9
Vervoort, I.10
Bender, H.11
Stucchi, M.12
Schaekers, M.13
Boullart, W.14
Van Hove, M.15
Vanhaelemeersch, S.16
Peterson, W.17
Shiota, A.18
Maex, K.19
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18
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8644266817
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Spin-on dielectric stack low-k integration with EB curing technology for 45 nm-node and beyond
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San Francisco
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Nagai H, Maekawa K, Iwashita M, Muramatsu M, Kubota K, Hinata K, Kokubo T, Shiota A, Hattori M, Nagano H, Tokushige K, Kodera M, Mishima K. Spin-on dielectric stack low-k integration with EB curing technology for 45 nm-node and beyond. Proc 2004 Int Interconnect Tech Conf, p 145-147, San Francisco.
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Proc 2004 Int Interconnect Tech Conf
, pp. 145-147
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Nagai, H.1
Maekawa, K.2
Iwashita, M.3
Muramatsu, M.4
Kubota, K.5
Hinata, K.6
Kokubo, T.7
Shiota, A.8
Hattori, M.9
Nagano, H.10
Tokushige, K.11
Kodera, M.12
Mishima, K.13
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