Cu/LKD-5109 damascene integration demonstration using FF-02 low-k spin-on hard-mask and embedded etch-stop

Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Volumn , Issue , 2002, Pages 51-53

  Kokubo, T ^a   Das, A ^b   Furukawa, Y ^c   Vos, I ^b   Iacopi, F ^b   Struyf, H ^b   Aelst, J V ^b   Maenhoudt, M ^b   Tokei, Z ^b   Vervoort, I ^b   Bender, H ^b   Stucchi, M ^b   Schaekers, M ^b   Boullart, W ^b   Van Hove, M ^b   Vanhaelemeersch, S ^b   Peterson, W ^e   Shiota, A ^a   Maex, K ^b,d  

^a JSR CORPORATION   (Japan)

^b IMEC   (Belgium)

^c PHILIPS RESEARCH LABORATORIES   (Netherlands)

^d UNIVERSITY OF LEUVEN   (Belgium)

^e JSR Electronics   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; CHEMICAL POLISHING; LOW-K DIELECTRIC;

CHEMICAL COMPATIBILITY; CHEMICAL MECHANICAL POLISHING(CMP); CHEMICAL VAPOR DEPOSITED; DAMASCENE INTEGRATION; MECHANICAL FILM PROPERTIES; MODEL SIMULATION; SPIN ON DIELECTRICS; SPIN-ON HARD MASKS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84961744604     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2002.1014884     Document Type: Conference Paper

References (3)

1. ITRS 2001 update, Semiconductor Industry Association, San Jose, CA, 2000
2. T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's", IEEE Transactions on Electron Devices, 40, 1993, pp. 118
3. D. De Roest et al, MAM 2000 proceedings, pp.82