Parametric minimum hardware QR-factoriser architecture for V-BLAST detection

IEE Proceedings: Circuits, Devices and Systems

Volumn 153, Issue 5, 2006, Pages 433-441

  Sobhanmanesh, F ^a   Nooshabadi, S ^a  

^a UNIVERSITY OF NEW SOUTH WALES   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DETECTORS; FIELD PROGRAMMABLE GATE ARRAYS; PARAMETER ESTIMATION; TRIANGULATION;

FPGA DEVICE; QR-FACTORISER; SQUARE MATRIX; V-BLAST DETECTION;

PROGRAM PROCESSORS;

EID: 33750462321     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20060060     Document Type: Article

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