Design and optimization of CMOS prescaler

2005 PhD Research in Microelectronics and Electronics - Proceedingsof the Conference

Volumn I, Issue , 2005, Pages 103-106

  Lei, Yu ^a,b   Koukab, Adil ^b   Declercq, Michel ^a,b  

^a IEEE   (Switzerland)

^b EPFL   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

BALANCED DYNAMIC LOAD TECHNIQUES; CMOS PRESCALERS; FREQUENCY RANGE;

DYNAMIC LOADS; ENERGY EFFICIENCY; FLIP FLOP CIRCUITS; LOGIC DESIGN; OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 33750291329     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RME.2005.1543021     Document Type: Conference Paper

References (7)

1. D-J Yang, Kenneth K.O, "A 14-Ghz 256/257 Dual- Modulus Prescaler with secondary Feedback and its application to monolithic CMOS 10.4GHZ PLL," IEEE Trans. on Microwave Theory and Techniques VOL.52, No.2, pp.461-468, Feb, 2004
2. HongmoWang, US Patent 6, 166, 571, Dec. 26. 2000
3. Hongmo Wang, "A 1.8v 3mw 16.8GHz Frequency Divider in 0.25um CMOS," in IEEE Int. Solid-state circuits Conf. Tech. Dig, San Francisco, CA, Feb. 2000, pp. 196-197
4. A. Shinmyo, M. Hashimoto, "Design and optimization of CMOS current mode logic dividers," 2004 IEEE AsiaPacific conference on Advanced system integrated circuits, 2004
5. Hans-Dieter Wohlmuth, Daniel Kehere, et. Al. "A 17GHz Dual-Modulus Prescaler in 120nm CMOS," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.479-482, 2003
6. Eric Touriner, Mathilde sie, Jacques Graffeuil, "A 14.5GHz 0.35um frequency divider for dualmodulus prescaler," IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp.227-230, 2002
7. Behzad Razavi, Kwing, F, Lee and Ran H, Yan, "Design of high-speed, low power frequency dividers and PLLs in deep submicron CMOS," IEEE J. Solid-state Circuits, Vol30, No.2, pp. 101-109, Feb, 1995.