A 14,5 GHz - 0,35 μm frequency divider for dual-modulus prescaler

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2002, Pages 227-230

  Tournier, Éric ^a   Sié, Mathilde ^a   Graffeuil, Jacques ^a  

^a LAAS CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FLIP FLOP CIRCUITS; LOGIC GATES; MASKS; MOSFET DEVICES;

DUAL-MODULUS PRESCALERS;

FREQUENCY DIVIDING CIRCUITS;

EID: 0036309632     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
2. High-speed divide-by-4/5 counter for a dual-modulus prescaler
3. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops
4. A sub-1mA 1.5-GHz silicon bipolar dual modulus prescaler
5. A low power 20 GHz SiGe dual-modulus prescaler
6. High-speed dual-modulus prescaler architecture for programmable digital frequency dividers