Design and optimization of CMOS current mode logic dividers

Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits

Volumn , Issue , 2004, Pages 434-435

  Shinmyo, Akinori ^a   Hashimoto, Masanori ^a,b   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT MODEL; FABRICATED CHIPS; LOGIC DIVIDERS; LOGIC VALUES;

AMPLIFIERS (ELECTRONIC); LOGIC DESIGN; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; OPTIMIZATION; TOPOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 14544274175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. Michael M. Green, et al.,"OC-192 Transmitter in Standard 0.18 μm CMOS," Proc. IEEE ISSCC, pp. 248-249, 2002.
2. Joseph M. C. Wong, Vincent S. L. Cheung and Howard C. Luong, "A 1-V 2.5-mW 5.2-GHz Frequency Divider in a 0.35-μm CMOS Process," IEEE J. Solid-State Circuits, vol. 38, pp. 1643-1648, Oct 2003.